The present invention relates, in general, to electronics, and more particularly, to semiconductor packages, structures thereof, and methods of forming semiconductor packages.
In the past, packaged power semiconductor devices utilized various manufacturing techniques to deposit conductive materials on exposed portions of conductive lead frames. In discrete power semiconductor devices, such as discrete field effect transistor (FET) semiconductor devices or diode semiconductor devices, manufacturers have utilized matrix lead frames that typically include an array of die attach pads each with a plurality of leads disposed proximate to but isolated from the die attach pads. Semiconductor die were attached to the die attach pads and electrically connected to the leads using discrete, stand-alone, or separated connective structures, such as wirebond interconnects or clips. This sub-assembly was then encapsulated to provide molded package bodies for each semiconductor die. Next, the encapsulated sub-assembly was placed in an electroplating apparatus and conductive material plated onto exposed surfaces of the conductive lead frames. During the electroplating process, current is passed through conductive leads, which reduces dissolved metal cations to form a thin coherent metal coating on exposed surfaces of the conductive lead frame.
One problem with this past approach is that in order for current to pass through the entire conductive lead frame, certain leads from adjoining sections of the lead frame must be joined together. After the electroplating process, the individually packaged semiconductor devices are then separated using a saw process. The saw process separates the joined leads thereby providing lead faces or flank surfaces without electroplated material. This leaves unwanted exposed lead frame material, which is typically copper. The exposed copper does not wet with solder, which produces weaker solder joints and detrimentally affects the reliability of assembled electronic components.
In attempt to address this problem, manufacturers have punched holes in the joined leads, created half-etched regions in the joined leads, or used side grooves in the joined leads to provide some side surface or flank surface coverage of the plated material. Although these approaches produced lead faces with between about 20% and 60% wettable surface coverage for these side or flank surfaces, these approaches cannot provide up to 100% coverage, and thus have still produced inferior solder joints. Also, these approaches have not provided strong enough solder joint protection at the assembly board level as required to fulfill stringent automotive specifications, which require 100% wettable flank coverage.
Accordingly, it is desirable to have a method and a structure that provides a packaged semiconductor device that improves the wettable surface coverage for side or flank surfaces of the lead frame. It is also desirable for the structure and method to be easily incorporated into manufacturing flows, and to be cost effective.